Icarus Verilog is designed to be extensible in a couple different dimensions. This leads to the possibilities of third-party extensions that I shall call ``plug-ins''.

Plug-ins may use the VPI interface to interface with the run-time simulation engine, or may be code generators that use the loadable target interface. The VPI interface to Icarus Verilog is a subset of the IEEE1364 PLI that is available with other Verilog compilers. Modules designed using PLI are useful for extending run-time behavior of the Verilog simulation. The loadable target interface is an Icarus Verilog API for writing code generators. Modules designed using this interface are useful for generating specific netlist formats, talking with different simulation engines, or other compile-time tasks.

The rest of this page contains links to various plug-ins that people have made available for Icarus Verilog. Some are actually stored on the Icarus FTP site, some are stored on the author's site. In either case, it is the author's task to maintain the particular package. If you don't yet know about Icarus Verilog, go <here>.

Simbus

This package supports distributed simulation of bus-based systems. It includes built in support for PCI bus and other bus type models, and support for models in Verilog and C/C++. More information is available at <http://iverilog.wikia.com/wiki/SIMBUS>

Image VPI

This VPI module provides simplified image I/O for Verilog programs. The source is available for download at <ftp://icarus.com/pub/eda/verilog/plug-ins/image-vpi>.

Pcisim

This package supports the development of test benches for PCI devices under test. The package includes simple models for typical host devices that would share a PCI device with the device under test, including a generic host processor. The latter includes an interface to a C API that allows software engineers, the device driver writers, to prototype device drivers for the device under test, and use those drivers to test the device. (This allows the software driver writers to become involved in the test of the device being designed.)

The source and binaries for some platforms are available for download at <ftp://icarus.com/pub/eda/pcisim>.

NOTE: This project has been replaced by Simbus described above. You probably want that instead, although pcisim is still available for legacy designs.

InFormal

InFormal connects Icarus Verilog to NuSMV for formal verification (aka. assertion based verification). The home page for Informal is <http://www.confluent.org/wiki/doku.php?id=informal:main>.

NOTE: Links to InFormal seem to be inoperative. I do not know if it has moved, or the project is dead. Contact me if the project is alive at a new home.

IVI

This used to be called "Icarus Verilog Interactive" but has grown beyond just Icarus Verilog. It is a graphical developer aid that supports a variety of simulators. It may require a few minor patches to Icarus Verilog to work, but the package includes those patches, so it seems complete on its own. The IVI home page is here: <http://ivi.sourceforge.net>.

There is a seperate project to maintain a MacOS X port of IVI, here: <http://ivionosx.sourceforge.net>.

Software Model Interface

The SMI is a PLI-based toolkit that uses VPI to implement a form of interprocess communication between Verilog programs and C++ programs. It is intended to be more convenient the the raw VPI, which can be quite a burden when non-trivial models are needed.

NOTE: Links to SMI seem to be dead, suggesting that it is no longer maintained. Let me know if that is incorrect.

Python/Perl Target Module

Icarus Verilog supports loading of target modules that take on the task of generating the desired output format. The Loadable Target API is a C API that allows programs to write these code generators. Pinhong Chen as written a loadable target module that offers Perl/Python support. So if you want to script your code generators, this module might help. <http://www-cad.eecs.berkeley.edu/~pinhong/scriptEDA/ >

VTracer

VTracer is a Verilog Testbench developer aid. It contains a Verilog-Perl co-simulation environment (based on TCP sockets), parsers (structural Verilog, VCD/dump),  and more. It's home page is here:  <http://vtracer.SourceForge.net>.

EDIF Target Module

This project by Vladimir Dergachev is a loadable target module, and associated libraries, for the support of EDIF output from Icarus Verilog. This is intended for synthesis, and he claims to support at least Atmel AT40K chips. See his sourceforge development page here: <http://volodya-project.sourceforge.net/tgt-edif.php >.

Note that this module has not been updated in a while, and the FPGA target to Icarus Verilog does most of its job.

Extract Hierarchy

This is a perl script to extract hierarchy from a set of Verilog source files. It is not really a plug-in to Icarus Verilog but a general tool that the author decided to make available. The file contains it its comments a description of usage and limitations. Download it from here: <ftp://icarus.com/pub/eda/verilog/plug-ins/extract-hier/ >